The various known techniques for making thin film transistors (TFTs), particularly the staggered type amorphous silicon (a-Si) thin film transistors, lead inevitably to causing the transistor gate or "grid" to be overlapped by its source and drain. The grid length 1a equals the summation of the channel length La, source/grid overlap 1s, and drain/grid overlap 1d, as shown in FIG. 1. The large grid length and the overlaps introduce stray capacitance, which increases the response time of the thin film transistor. Hence, the operation frequency of the a-Si logic integrated circuit is restrained. Moreover, because of the charge redistribution between the stray capacitance and the load capacitance, the signal on the grid can couple to the load. This effect can introduce an unacceptable DC voltage level when these components are used in liquid crystal display devices, and cause a voltage shift when these components are used in logic integrated circuits. In order to reduce the charge redistribution effect, a storage capacitor is connected in parallel with the liquid crystal cell of logic integrated circuit (the load). However, the parallel storage capacitor reduces the operating speed of the transistor and it can restrain the number of scan line in liquid crystal display.
Recently many new thin film transistor manufacturing processes for metal insulator semiconductor field effect transistors (MISFETs) have been proposed enabling the transistor grid to be aligned with the drain and source, thus eliminating the overlap capacitances almost entirely. Such processes have been described in the article in IEEE Electron Device Letters, Vol. EDL-3, No. 7 (July 1982), entitled "A Self-Alignment Process for Amorphous Silicon Thin Film Transistors," by T. Kodama et al. and in U.S. Pat. No. 4,587,720 (May 13, 1986) entitled "Process for the Manufacture of a Self-Aligned Thin-Film Transistor" by Chenevas-Paule et al. These manufacturing techniques employ a photoresist lift-off process to form the source and drain regions. When the lift-off process is used to fabricate the a-Si thin film transistors, the n+ a-Si layer is deposited on photoresist. The deposition temperature of the n+ a-Si layer is higher than 200.degree. C., and therefore a high temperature photoresist must be used.
The a-Si metal semiconductor field effect transistor (MESFET) was also fabricated. There is a space between the grid and the source (or drain) of the MESFET. Therefore, the stray capacitance can be eliminated entirely. Such a device was described in an article in the Japanese Journal of Applied Physics, Vol. 24, No. 8 (Aug., 1985), pp. L632-L634, entitled "MES-FETs Fabricated on Doped a-Si Films" by K. Okamoto et al. However, the thickness of the active layer is very critical. With too thick an active layer, the FET cannot be switched off. With too thin an active layer, the on-current and the transconductance of the FET degrade drastically. Moreover, the high leakage current and low breakdown voltage of the a-Si Schottky gate diode make the device exhibit high gate current and low operation gate voltage, causing the transistor to exhibit a high off-current.